Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods for fabricating local isolation formations for finFET devices.
Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure.
FinFET designs use “fins” that may be formed on the surface of a semiconductor wafer using selective-etching processes. The fins may be used to form a raised channel between the gate and the source and drain of a transistor. The gate is then deposited such that it wraps around the fin to form a trigate structure. Since the channel is extremely thin, the gate would generally have a greater control over the carriers within. However, when the transistor is switched on, the shape of the channel may limit the current flow. Therefore, multiple fins may be used in parallel to provide greater current flow for increased drive strength.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art FinFET device. A FinFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The semiconductor device may be position to a vertical orientation, creating one or more fins 110. The source and drain of the FinFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length of the FinFET device. The current flow occurs along an orthogonal crystal plane in a direction parallel to the plane of the semiconductor wafer. The electrically significant height of the fin (labeled H) is typically determined by the amount of oxide recess in the fin reveal step and hence is constant for all fins 110.
The thickness of the fin (labeled Tfi) determines the short channel behavior of the transistor device and is usually small in comparison with the height H of the fin 110. The pitch (labeled P) of the fins is determined by lithographic constraints and dictates the wafer area to implement the desired device width. A small value of the pitch P and a large value of the height H enable a better packing of the devices per square area resulting in a denser design, or more efficient use of silicon wafer area.
There is a push to scale down integrated circuits to support ever-shrinking electronic devices. This has prompted designers to reduce the size of finFET devices. As such, the pitch of the fin in finFET devices are reduced. However, as fin pitch is reduced, it becomes more difficult to fill the spaces between fins when processing finFET devices. Further, as new channel-materials (e.g., SiGe III-V material) are used in processing of finFET devices, thicker liner materials are required in order to prevent channel FIN critical dimension (CD) loss due to oxidation. However, the need for reducing fin pitch in direct contravention to the requirement of thicker liner material. FIGS. 2 and 3 illustrate these issues.
FIG. 2 shows a stylized depiction of a typical set of fins in a finFET device, between which, a liner material is deposited. FIG. 3 illustrates a stylized depiction of a typical set of fins that has experienced fin CD loss. A set of fins 210 are formed within an insulation material 215 (e.g., flowable oxide material (F-OX)). The fins 210 are formed over a substrate 205. Prior to covering the fins with an Oxide, a liner 220 is formed around fins 210. It is desirable to deposit F-OX between the fins 210. However, due to the small pitch (e.g., 50 nm) between the fins 210, an oxide void may be formed between the fins 210. It is increasingly difficult to fill the voids that form between the fins 210.
Further, due to the problems in filling the voids using state of the art processing, higher temperatures during processing is required for densification (densification anneal process). If there is a void between the fins, the fins may not be properly protected during subsequent processing, such as annealing process. If the protection material, e.g., nitride, is not deposited deep into the void between the fins, then oxidization of the fin structure could occur. In some cases, the liner 220 may not be thick enough in the voids, therefore offering less protection during a steam anneal process for the F-OX material. As a result of the lack of protection due to the line 220 being too thin during the steam anneal process performed for the F-OX, a loss of fin critical dimension (CD) 310 caused by oxidization can occur, as exemplified in FIG. 3. This could result in process errors and device performance problems.
The void formation between the fins 210 can cause downstream process problems. These downstream process problems include issues regarding dummy poly gate formation or replacement gate formation. Metal “subways” through the voids may develop. These metal subways may cause electrical shorts in various portions of the semiconductor device being manufactured.
The present disclosure may address and/or at least reduce one or more of the problems identified above.